#ifndef C8051F120_REG_DEF_H
#define C8051F120_REG_DEF_H 
/*---------------------------------------------------------------------------
;	c8051f120.h - The Device Register Definition 
;
;	Copyright (C) 2007 Our AMCT Corp.
; 	All rights reserved.
;	
;	License Type:	BSD
;	
;	Author:			Xu Chenxiang
;	File Version:	v0.1 (2007/07/11)
;	
;	File History:
;	v0.1 	Inital Release
;
; 	TARGET MCUs	: C8051F120, 'F121, 'F122, 'F123, 'F124, 'F125, "F126, 'F127
;
;---------------------------------------------------------------------------*/


// External Memory Interface Definition EMI0_PAGE = 0
#ifdef XRAM_INSTALL
// EMIF Control Register (1)
/* EMI0CN - External Memory Interface Control
Register Name :EMI0CN
Bit Name :PGSEL
Usage : XRAM Page Select Bits
The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM.
0x00: 0x0000 to 0x00FF
0x01: 0x0100 to 0x01FF
...
0xFE: 0xFE00 to 0xFEFF
0xFF: 0xFF00 to 0xFFFF
*/

// EMIF Control Register (2)
/* EMI0CF - External Memory Configuration */
#define PRTSEL 5							// EMIF Port Select (EMI0CF.PRTSEL)
#define PRTSEL_P0_P3 0						// EMIF active on P0~P3
#define PRTSEL_P4_P7 1						// EMIF active on P4~P7

#define EMD2 4								// EMIF Multiplex Mode Select
#define EMD2_MUL 0							// EMIF operates in multiplexed address/data mode.
#define EMD2_NON_MUL 1						// EMIF operates in non-multiplexed mode (separate address and data pins).

#define EMD1_EMD0 2							// EMIF Oerating Mode Select
#define EMD1_EMD0_INTERNAL 0x00				// Internal Only
#define EMD1_EMD0_SPLIT_WITHOUT_BANK 0x01	// Split Mode without Bank Select
#define EMD1_EMD0_SPLIT_WITH_BANK 0x02				// Split Mode with Bank Select
#define EMD1_EMD0_EXTERNAL 0x03				// External Only

#define EALE1_EALE0 0						// EMIF ALE Pulse-Width Select Bits
#define EALE1_EALE0_CLK1 0x00				// ALE high and ALE low pulse width=1 SYSCLK cycle.
#define EALE1_EALE0_CLK2 0x01				// ALE high and ALE low pulse width=2 SYSCLK cycle.
#define EALE1_EALE0_CLK3 0x02				// ALE high and ALE low pulse width=3 SYSCLK cycle.
#define EALE1_EALE0_CLK4 0x03				// ALE high and ALE low pulse width=4 SYSCLK cycle.

// EMIF Control Register (3)
/* EMI0TC - External Memory Timing Control */
#define EAS1_EAS0 6							// EMIF Address Setup Time Bits.
#define EAS1_EAS0_CLK0 0x00					// Address setup time=0 SYSCLK cycles.
#define EAS1_EAS0_CLK1 0x01					// Address setup time=1 SYSCLK cycles.
#define EAS1_EAS0_CLK2 0x02					// Address setup time=2 SYSCLK cycles.
#define EAS1_EAS0_CLK3 0x03					// Address setup time=3 SYSCLK cycles.

#define EWR3_EWR0 2							//EMIF /WR and /RD Pulse-Width Control Bits
#define EWR3_EWR0_CLK1 0x00					//0000: /WR and /RD pulse width=1 SYSCLK cycle.
#define EWR3_EWR0_CLK2 0x01					//0001: /WR and /RD pulse width=2 SYSCLK cycles.
#define EWR3_EWR0_CLK3 0x02					//0010: /WR and /RD pulse width=3 SYSCLK cycles.
#define EWR3_EWR0_CLK4 0x03					//0011: /WR and /RD pulse width=4 SYSCLK cycles.
#define EWR3_EWR0_CLK5 0x04					//0100: /WR and /RD pulse width=5 SYSCLK cycles.
#define EWR3_EWR0_CLK6 0x05					//0101: /WR and /RD pulse width=6 SYSCLK cycles.
#define EWR3_EWR0_CLK7 0x06					//0110: /WR and /RD pulse width=7 SYSCLK cycles.
#define EWR3_EWR0_CLK8 0x07					//0111: /WR and /RD pulse width=8 SYSCLK cycles.
#define EWR3_EWR0_CLK9 0x08					//1000: /WR and /RD pulse width=9 SYSCLK cycles.
#define EWR3_EWR0_CLK10 0x09				//1001: /WR and /RD pulse width=10 SYSCLK cycles.
#define EWR3_EWR0_CLK11 0x0A				//1010: /WR and /RD pulse width=11 SYSCLK cycles.
#define EWR3_EWR0_CLK12 0x0B				//1011: /WR and /RD pulse width=12 SYSCLK cycles.
#define EWR3_EWR0_CLK13 0x0C				//1100: /WR and /RD pulse width=13 SYSCLK cycles.
#define EWR3_EWR0_CLK14 0x0D				//1101: /WR and /RD pulse width=14 SYSCLK cycles.
#define EWR3_EWR0_CLK15 0x0E				//1110: /WR and /RD pulse width=15 SYSCLK cycles.
#define EWR3_EWR0_CLK16 0x0F				//1111: /WR and /RD pulse width=16 SYSCLK cycles.

#define EAH1_EAH0 0							// EMIF Address Hold Time Bits.
#define EAH1_EAH0_CLK0 0x00					// Address Hold time=0 SYSCLK cycles.
#define EAH1_EAH0_CLK1 0x01					// Address Hold time=1 SYSCLK cycles.
#define EAH1_EAH0_CLK2 0x02					// Address Hold time=2 SYSCLK cycles.
#define EAH1_EAH0_CLK3 0x03					// Address Hold time=3 SYSCLK cycles.

#endif

// Cross Bar Multiplex Definition 
// Cross Bar Multiplex (1)
/* XBR0: Port I/O Crossbar Register 0 */
#define CP0E 7								// Comparator 0 Output Enable Bit
#define CP0E_NO 0							// CP0 unrouted to Port pin
#define CP0E_YES 1							// CP0 routed to Port pin

#define ECI0E 6								// PCA0 External Counter Input Enable Bit
#define ECI0E_NO 0							// External Counter Input unavailable at Port pin
#define ECI0E_YES 1							// External Counter Input routed to Port pin

#define PCA0ME 3							// PCA0 Mdule I/O Enable Bits
#define PCA0ME_NONE 0						// All PCA0 I/O unavailable at port pins
#define PCA0ME_CEX0 1						// CEX0 routed to port pin
#define PCA0ME_CEX0_CEX1 2					// CEX0, CEX1 routed to 2 port pins.
#define PCA0ME_CEX0_CEX1_CEX2 3				// PCA0ME_CEX0_CEX1_CEX2 routed to 3 port pins
#define PCA0ME_CEX0_CEX1_CEX2_CEX3 4		// PCA0ME_CEX0_CEX1_CEX2_CEX3 routed to 4 port pins
#define PCA0ME_CEX0_CEX1_CEX2_CEX3_CEX4 5	// PCA0ME_CEX0_CEX1_CEX2_CEX3_CEX4 routed to 5 port pins
#define PCA0ME_CEX0_CEX1_CEX2_CEX3_CEX4_CEX5 6	//PCA0ME_CEX0_CEX1_CEX2_CEX3_CEX4_CEX5 routed to 6 port pins

#define UART0EN 2							// UART 0 Output Enable Bit
#define UART0EN_NO 0						// UART 0 Output Disable
#define UART0EN_YES 1						// UART 0 Output Enable

#define SPI0EN 1							// SPI 0 Output Enable Bit
#define SPI0EN_NO 0							// SPI 0 Output Disable
#define SPI0EN_YES 1						// SPI 0 Output Enable

#define SMB0EN 0							// SMBus0 Bus I/O Enable Bit
#define SMB0EN_NO 0							// SMBus0 Disable
#define SMB0EN_YES 1						// SMBus0 Enable

// Cross Bar Multiplex (2)
/* XBR1: Port I/O Crossbar Register 1 */
#define SYSCKE 7							//SYSCLK Output Enable Bit
#define SYSCKE_NO 0							//SYSCLK Output Disable
#define SYSCKE_YES 1						//SYSCLK Output Enable

#define T2EXE 6								//T2EXE Output Enable Bit
#define T2EXE_NO 0							//T2EXE Output Disable
#define T2EXE_YES 1							//T2EXE Output Enable

#define T2E 5								//T2E Output Enable Bit
#define T2E_NO 0							//T2E Output Disable
#define T2E_YES 1							//T2E Output Enable

#define INT1E 4								//INT1E Output Enable Bit
#define INT1E_NO 0							//INT1E Output Disable
#define INT1E_YES 1							//INT1E Output Enable

#define T1E 3								//T1E Output Enable Bit
#define T1E_NO 0							//T1E Output Disable
#define T1E_YES 1							//T1E Output Enable

#define INT0E 2								//INT0E Output Enable Bit
#define INT0E_NO 0							//INT0E Output Disable
#define INT0E_YES 1							//INT0E Output Enable

#define T0E 1								//T0E Output Enable Bit
#define T0E_NO 0							//T0E Output Disable
#define T0E_YES 1							//T0E Output Enable

#define CP1E 0								//CP1E Output Enable Bit
#define CP1E_NO 0							//CP1E Output Disable
#define CP1E_YES 1							//CP1E Output Enable

// Cross Bar Multiplex (3)
/* XBR2: Port I/O Crossbar Register 2 */
#define WEAKPUD 7							//Weak Pullup Disable Bit
#define WEAKPUD_NO 0						//Weak pullups globally enabled
#define WEAKPUD_YES 1						//Weak pullups globally disabled

#define XBARE 6								//Crossbar Enable Bit
#define XBARE_NO 0							//XBARE Output Disable
#define XBARE_YES 1							//XBARE Output Enable

#define CNVST2E 5							//External Convert Start 2 Input Enable Bit.
#define CNVST2E_NO 0						//CNVST2E Output Disable
#define CNVST2E_YES 1						//CNVST2E Output Enable

#define T4EXE 4								//T4EX Input Enable Bit
#define T4EXE_NO 0							//T4EXE Output Disable
#define T4EXE_YES 1							//T4EXE Output Enable

#define T4E 3								//T4 Input Enable Bit
#define T4E_NO 0							//T4E Output Disable
#define T4E_YES 1							//T4E Output Enable

#define UART1E 2							//UART1 I/O Enable Bit
#define UART1E_NO 0							//UART1E Output Disable
#define UART1E_YES 1						//UART1E Output Enable

#define EMIFLE 1							//External Memory Interface Low-Port Enable Bit
#define EMIFLE_NO 0							//EMIFLE Output Disable
#define EMIFLE_YES 1						//EMIFLE Output Enable

#define CNVST0E 0							//ADC0 External Convert Start Input Enable Bit
#define CNVST0E_NO 0						//CNVST0E Output Disable
#define CNVST0E_YES 1						//CNVST0E Output Enable










#endif